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? 2004 microchip technology inc. ds21908a-page 1 mcp6s91/2/3 features ? multiplexed inputs: 1 or 2 channels ? 8 gain selections: - +1, +2, +4, +5, +8, +10, +16 or +32 v/v ? serial peripheral interface (spi ? ) ? rail-to-rail input and output ? low gain error: 1% (max.) ? offset mismatch between channels: 0 v ? high bandwidth: 1 to 18 mhz (typ.) ? low noise: 10 nv/ hz @ 10 khz (typ.) ? low supply current: 1.0 ma (typ.) ? single supply: 2.5v to 5.5v ? extended temperature range: -40c to +125c typical applications ? a/d converter driver ? multiplexed analog applications ? data acquisition ? industrial instrumentation ? test equipment ? medical instrumentation block diagram description the microchip technology inc. mcp6s91/2/3 are analog programmable gain amplifiers (pgas). they can be configured for gains from +1 v/v to +32 v/v and the input multiplexer can select one of up to two chan- nels through a spi port. the serial interface can also put the pga into shutdown to conserve power. these pgas are optimized for high-speed, low offset voltage and single-supply operation with rail-to-rail input and output capability. these specifications support single- supply applications needing flexible performance or multiple inputs. the one-channel mcp6s91 and the two-channel mcp6s92 are available in 8-pin pdip, soic and msop packages. the two-channel mcp6s93 is available in a 10-pin msop package. all parts are fully specified from -40c to +125c. package types v out v ref v dd cs si so sck ch1 ch0 v ss 8 r f r g mux spi? logic gain switches resistor ladder (r lad ) v ref ch0 v ss si sck 12 3 4 8 76 5 v dd cs v out mcp6s91 pdip, soic, msop ch1 ch0 v ss si sck 12 3 4 8 76 5 v dd cs v out mcp6s92 pdip, soic, msop ch0 v out ch1 cs 12 3 4 10 98 7si sck 56 v ref v dd so v ss mcp6s93 msop single-ended, rail-to-rail i/o, low-gain pga downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 2 mcp6s91/2/3 1.0 electrical characteristics absolute maximum ratings ? v dd Cv ss ........................................................................7.0v all inputs and outputs..................... v ss C0.3vtov dd +0.3v difference input voltage ....................................... |v dd Cv ss | output short circuit current ..................................continuous current at input pin ............................................................. 2ma current at output and supply pins ................................ 30 ma storage temperature .....................................-65c to + 150c junction temperature .......................................... ........ +150c esd protection on all pins (hbm; mm) ................ 4 kv; 200v ? notice: stresses above those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this sp ecification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. pin function table name function v out analog output ch0, ch1 analog inputs v ref external reference pin v ss negative power supply cs spi chip select si spi serial data input so spi serial data output sck spi clock input v dd positive power supply dc characteristics electrical specifications: unless otherwise indicated, t a = +25c, v dd = +2.5v to +5.5v, v ss = gnd, v ref = v ss , g = +1 v/v, input = ch0 = (0.3v)/g, ch1 = 0.3v, r l =10k to v dd /2, si and sck are tied low and cs is tied high. parameters sym min typ max units conditions amplifier inputs (ch0, ch1) input offset voltage v os -4 +4 mv g = +1 input offset voltage mismatch ? v os 0 v between inputs (ch0, ch1) input offset voltage drift ? v os / ? t a 1 . 8 v / ct a = -40c to +125c power supply rejection ratio psrr 70 90 db g = +1 (note 1) input bias current i b 1 pa chx = v dd /2 input bias current at temperature i b 30 pa chx = v dd /2, t a = +85c i b 600 pa chx = v dd /2, t a = +125c input impedance z in 1 0 13 ||7 ||pf input voltage range v ivr v ss ? 0.3 v dd + 0.3 v (note 2) reference input (v ref ) input impedance z in_ref (5/g)||6 k ||pf voltage range v ivr_ref v ss v dd v (note 2) amplifier gain nominal gains g 1 to 32 v/v +1, +2, +4, +5, +8, +10, +16 or +32 dc gain error g = +1 g e -0.2 +0.2 % v out 0.3v to v dd ? 0.3v g +2 g e -1.0 +1.0 % v out 0.3v to v dd ? 0.3v dc gain drift g = +1 ? g/ ? t a 0.0002 %/c t a = -40c to +125c g +2 ? g/ ? t a 0.0004 %/c t a = -40c to +125c note 1: r lad (r f +r g in figure 4-1) connects v ref , v out and the inverting input of the internal amplifier. the mcp6s92 has v ref tied internally to v ss , so v ss is coupled to the internal amplifier and t he psrr spec describes psrr+ only. it is recommended that the mcp6s92s v ss pin be tied directly to ground to avoid noise problems. 2: the mcp6s92s v ivr and v ivr_ref are not tested in production; they are set by design and characterization. 3: i q includes current in r lad (typically 60 a at v out = 0.3v). both i q and i q_shdn exclude digital switching currents. downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 3 mcp6s91/2/3 ladder resistance ladder resistance r lad 3.4 4.9 6.4 k (note 1) ladder resistance across temperature ? r lad / ? t a + 0 . 0 2 8 % / ct a = -40c to +125c (note 1) amplifier output dc output non-linearity g = +1 v onl 0.18 % of fsr v out 0.3v to v dd ? 0.3v, v dd =5.0v g +2 v onl 0.050 % of fsr v out 0.3v to v dd ? 0.3v, v dd =5.0v maximum output voltage swing v oh_ana , v ol_ana v ss + 20 v dd C 100 mv g +2; 0.5v output overdrive v ss + 60 v dd C 60 g +2; 0.5v output overdrive, v ref = v dd /2 short circuit current i sc 2 5 m a power supply supply voltage v dd 2.5 5.5 v minimum valid supply voltage v dd_val 0.4 2.0 v register data still valid quiescent current i q 0.4 1.0 1.6 ma i o = 0 (note 3) quiescent current, shutdown mode i q_shdn 3 0 p ai o = 0 (note 3) dc characteristics (continued) electrical specifications: unless otherwise indicated, t a = +25c, v dd = +2.5v to +5.5v, v ss = gnd, v ref = v ss , g = +1 v/v, input = ch0 = (0.3v)/g, ch1 = 0.3v, r l =10k to v dd /2, si and sck are tied low and cs is tied high. parameters sym min typ max units conditions note 1: r lad (r f +r g in figure 4-1) connects v ref , v out and the inverting input of the internal amplifier. the mcp6s92 has v ref tied internally to v ss , so v ss is coupled to the internal amplifier and t he psrr spec describes psrr+ only. it is recommended that the mcp6s92s v ss pin be tied directly to ground to avoid noise problems. 2: the mcp6s92s v ivr and v ivr_ref are not tested in production; they are set by design and characterization. 3: i q includes current in r lad (typically 60 a at v out = 0.3v). both i q and i q_shdn exclude digital switching currents. downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 4 mcp6s91/2/3 ac characteristics electrical specifications: unless otherwise indicated, t a = +25c, v dd = +2.5v to +5.5v, v ss = gnd, v ref = v ss , g = +1 v/v, input = ch0 = (0.3v)/g, ch1 = 0.3v, r l =10k to v dd /2, c l = 60 pf, si and sck are tied low and cs is tied high. parameters sym min typ max units conditions frequency response -3 db bandwidth bw 1 to 18 mhz all gains; v out < 100 mv p-p (note 1) gain peaking gpk 0 db all gains; v out < 100 mv p-p total harmonic distortion plus noise f = 20 khz, g = +1 v/v thd+n 0.0011 % v out = 1.5v 1.0 v pk , v dd = 5.0v, bw = 80 khz, r l = 10 k to 1.5v f = 20 khz, g = +1 v/v thd+n 0.0089 % v out = 2.5v 1.0 v pk , v dd = 5.0v, bw = 80 khz f = 20 khz, g = +4 v/v thd+n 0.0045 % v out = 2.5v 1.0 v pk , v dd = 5.0v, bw = 80 khz f = 20 khz, g = +16 v/v thd+n 0.028 % v out = 2.5v 1.0 v pk , v dd = 5.0v, bw = 80 khz step response slew rate sr 4.0 v/s g = 1, 2 11 v/s g = 4, 5, 8, 10 22 v/s g = 16, 32 noise input noise voltage e ni 4 . 5 v p-p f = 0.1 hz to 10 hz (note 2) 30 f = 0.1 hz to 200 khz (note 2) input noise voltage density e ni 1 0n v / hz f = 10 khz (note 2) input noise current density i ni 4 f a / hz f = 10 khz note 1: see table 4-1 for a list of typical numbers and fi gure 2-25 for the frequency response versus gain. 2: e ni and e ni include ladder resistance noise. see figure 2-12 for e ni versus g data. downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 5 mcp6s91/2/3 digital characteristics electrical specifications: unless otherwise indicated, t a = 25c, v dd = +2.5v to +5.5v, v ss = gnd, v ref = v ss , g = +1 v/v, input = ch0 = (0.3v)/g, ch1 = 0.3v, r l =10k to v dd /2, c l = 60 pf, si and sck are tied low and cs is tied high. parameters sym min typ max units conditions spi inputs (cs , si, sck) logic threshold, low v il 0 0.3v dd v input leakage current i il -1.0 +1.0 a logic threshold, high v ih 0.7 v dd v dd v amplifier output leakage current -1.0 1.0 a in shutdown mode spi output (so, for mcp6s93) logic threshold, low v ol_dig v ss v ss +0.4 v i ol = 2.1 ma, v dd = 5v logic threshold, high v oh_dig v dd C 0.5 v dd vi oh = -400 a spi timing pin capacitance c pin 10 pf all digital i/o pins input rise/fall times (cs , si, sck) t rfi 2 s (note 1) output rise/fall times (so) t rfo 5n s mcp6s93 cs high time t csh 40 ns sck edge to cs fall setup time t cs0 10 ns sck edge when cs is high cs fall to first sck edge setup time t cssc 40 ns sck frequency f sck 1 0m h z v dd = 5v (note 2) sck high time t hi 40 ns sck low time t lo 40 ns sck last edge to cs rise setup time t sccs 30 ns cs rise to sck edge setup time t cs1 100 ns sck edge when cs is high si setup time t su 40 ns si hold time t hd 10 ns sck to so valid propagation delay t do 80 ns mcp6s93 cs rise to so forced to zero t soz 80 ns mcp6s93 channel and gain select timing channel select time t ch 1.5 s chx = 0.6v, chy = 0.3v, g = 1, chx to chy select, cs = 0.7 v dd to v out 90% point gain select time t g 1 s chx = chy = 0.3v, g = 5 to g = 1 select, cs = 0.7 v dd to v out 90% point shutdown mode timing out of shutdown mode (cs goes high) to amplifier output turn-on time t on 3 . 51 0 sc s = 0.7 v dd to v out 90% point into shutdown mode (cs goes high) to amplifier output high-z turn-off time t off 1 . 5 sc s = 0.7 v dd to v out 90% point note 1: not tested in production. set by design and characterization. 2: when using the device in the daisy-chain configuration, maximum clock frequency is determined by a combination of propagation delay time (t do 80 ns), data input set-up time (t su 40 ns), sck high time (t hi 40 ns) and sck rise and fall times of 5 ns. maximum f sck is therefore 5.8 mhz. downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 6 mcp6s91/2/3 temperature characteristics electrical specifications: unless otherwise indicated, v dd = +2.5v to +5.5v, v ss = gnd. parameters sym min typ max units conditions temperature ranges specified temperature range t a -40 +125 c (note 1) operating temperature range t a -40 +125 c storage temperature range t a -65 +150 c thermal package resistances thermal resistance, 8l-pdip ja 8 5 c / w thermal resistance, 8l-soic ja 1 6 3 c / w thermal resistance, 8l-msop ja 2 0 6 c / w thermal resistance, 10l-msop ja 1 4 3 c / w note 1: operation in this range must not cause t j to exceed maximum junction temperature (+150c). downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 7 mcp6s91/2/3 figure 1-1: channel select timing diagram. figure 1-2: pga shutdown timing diagram (must enter correct commands before cs goes high). figure 1-3: gain select timing diagram. figure 1-4: detailed spi? serial interface timing; spi 0,0 mode. cs v out t ch 0.6v 0.3v cs t off v out t on hi-z hi-z i ss 30 pa (typ.) 1.0 ma (typ.) 0.3v cs v out t g 1.5v 0.3v cs sck si t su t hd t cssc t sccs t csh so (first 16 bits out are always zeros) t do t soz t lo t hi 1/f sck t cs0 t cs1 downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 8 mcp6s91/2/3 figure 1-5: detailed spi? serial interface timing; spi 1,1 mode. 1.1 dc output voltage specs / model 1.1.1 ideal model the ideal pga output voltage (v out ) is: equation 1-1: (see figure 1-6). this equation holds when there are no gain or offset errors and when the v ref pin is tied to a low-impedance source (<< 0.1 ) at ground potential (v ss = 0v). 1.1.2 linear model the pgas linear region of operation, including offset and gain errors, is modeled by the line v o_lin shown in figure 1-6. equation 1-2: the end points of this line are at v o_id = 0.3v and v dd C 0.3v. figure 1-6 shows the relationship between the gain and offset specifications referred to in the electrical specifications as follows: equation 1-3: the dc gain drift ( ? g/ ? t a ) can be calculated from the change in g e across temperature. this is shown in the following equation: equation 1-4: cs sck si t su t hd t cssc t sccs so (first 16 bits out are always zeros) t do t soz t hi t lo 1/f sck t cs1 t csh t cs0 where: g is the nominal gain v o_id g vin = v ref v ss 0v == v o_lin g1 g e + () v in 0.3v g ----------- v os + C ?? ?? 0.3v + = v ref v ss 0v == g e 100% v 2 v 1 C gv dd 0.6v C () ------------------------------------- - = v os v 1 g1 g e + () ------------------------ - = g+1 = g ? t a ?M g e ? t a ? --------- - = downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 9 mcp6s91/2/3 figure 1-6: output voltage model with the standard condition v ref =v ss =0v. 1.1.3 output non-linearity figure 1-7 shows the integral non-linearity (inl) of the output voltage. equation 1-5: the output non-linearity specification in the electrical specifications (with units of: % of fsr) is related to figure 1-7 by: equation 1-6: the full-scale range (fsr) is v dd C 0.6v (0.3v to v dd C 0.3v). figure 1-7: output voltage inl with the standard condition v ref =v ss =0v. 1.1.4 different v ref conditions some of the plots in section 2.0 typical performance curves , have the conditions v ref =v dd /2 or v ref =v dd . the equations and figures above are easily modified for these conditions. the ideal v out equation becomes: equation 1-7: the complete linear model is: equation 1-8: where the new v in end points are: equation 1-9: the equations for extracting the specifications do not change. 0 0 0.3 v dd C 0.3 v dd v o u t v out (v) v in (v) 0.3 v dd C 0.3 v dd g gg v 1 v o _ i d v o _ l i n v 2 inl v out v o_lin C = v onl max v 3 v 4 , () v dd 0.6v C ------------------------------ - 100% ? = 0 inl (v) v in (v) 0.3 v dd C 0.3 v dd g gg 0 v 3 v 4 v o_id v ref gv in v ref C () + = v dd v ref v ss 0v = > v on_lin g1 g e + () v in v in_l v os + C () 0.3v + = v ref v ss 0v == v in_l 0.3v v ref C g ------------------------------ v ref + = v in_h v dd 0.3v C v ref C g ----------------------------------------------- v ref + = downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 10 mcp6s91/2/3 2.0 typical performance curves note: unless otherwise indicated, t a = +25c, v dd = +2.5v to +5.5v, v ss = gnd, v ref =v ss , g = +1 v/v, input = ch0 = (0.3v)/g, ch1 = 0.3v, r l =10k to v dd /2 and c l = 60 pf. figure 2-1: dc gain error, g = +1. figure 2-2: dc gain error, g +2. figure 2-3: ladder resistance drift. figure 2-4: dc gain drift, g = +1. figure 2-5: dc gain drift, g +2. figure 2-6: crosstalk vs. frequency (circuit in figure 6-4). note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% 20% 22% 24% -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 dc gain error (%) percentage of occurrences 600 samples g = +1 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.00.1 0.2 0.3 0.4 0.5 0.6 dc gain error (%) percentage of occurrences 600 samples g +2 0% 2% 4% 6% 8% 10% 12% 14% 16% 0.019 0.020 0.021 0.022 0.023 0.024 0.025 0.026 0.027 0.028 0.029 0.030 ladder resistance drift (%/c) percentage of occurrences 597 samples t a = -40 to +125c 0% 5% 10% 15% 20% 25% 30% 35% -0.0006 -0.0005 -0.0004 -0.0003 -0.0002 -0.0001 0.0000 0.0001 0.0002 0.0003 0.0004 0.0005 0.0006 dc gain drift (%/c) percentage of occurrences 600 samples g = +1 t a = -40 to +125c 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% 20% 22% 24% 26% -0.0020 -0.0016 -0.0012 -0.0008 -0.0004 0.0000 0.0004 0.0008 0.0012 0.0016 0.0020 dc gain drift (%/c) percentage of occurrences 600 samples g +2 t a = -40 to +125c -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 1.e+05 1.e+06 1.e+07 1.e+0 8 frequency (hz) crosstalk, input referred (db) v dd = 5.0v g = +32 v/v ch0 selected r s = 1 k r s = 0 r s = 100 r s = 10 k 100k 100m 10m 1m downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 11 mcp6s91/2/3 note: unless otherwise indicated, t a = +25c, v dd = +2.5v to +5.5v, v ss = gnd, v ref =v ss , g = +1 v/v, input = ch0 = (0.3v)/g, ch1 = 0.3v, r l =10k to v dd /2 and c l = 60 pf. figure 2-7: input offset voltage, v dd =4.0v. figure 2-8: input offset voltage mismatch. figure 2-9: input noise voltage density vs. frequency. figure 2-10: input offset voltage drift. figure 2-11: input offset voltage vs. v ref voltage. figure 2-12: input noise voltage density vs. gain. 0% 5% 10% 15% 20% 25% 30% -3 -2 -1 0 1 2 3 input offset voltage (mv) percentage of occurrences 600 samples g = +1 v dd = 4.0v 0% 5% 10% 15% 20% 25% 30% 35% -30-20 -10 0 1020 30 input offset voltage mismatch (v) percentage of occurrences 32 samples v dd = 5.5v v in = 0.3v = 10.0 v rms measurement repeatability: 10.4 v rms 1 10 100 1000 0.1 1 10 100 1000 10000 100000 frequency (hz) input noise voltage density (nv/ ? hz) 1k 10k 100k 1 10 100 0.1 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% 20% 22% 24% -10 -8-6 -4 -2 02 4 6 8 10 input offset voltage drift (v/c) percentage of occurrences 600 samples t a = -40 to +125c g = +1 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v ref voltage (v) input offset voltage (mv) v dd = 5.5v v dd = 2.5v g = +1v in = v ref 0 1 2 3 4 5 6 7 8 9 10 11 12 13 12458101632 gain (v/v) input noise voltage density (nv/ ? hz) f = 10 khz downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 12 mcp6s91/2/3 note: unless otherwise indicated, t a = +25c, v dd = +2.5v to +5.5v, v ss = gnd, v ref =v ss , g = +1 v/v, input = ch0 = (0.3v)/g, ch1 = 0.3v, r l =10k to v dd /2 and c l = 60 pf. figure 2-13: psrr vs. ambient temperature. figure 2-14: input bias current vs. ambient temperature. figure 2-15: quiescent current in shutdown mode vs. ambient temperature. figure 2-16: psrr vs. frequency. figure 2-17: input bias current vs. input voltage. figure 2-18: quiescent current in shutdown mode. 70 80 90 100 110 120 -50 -25 0 25 50 75 100 125 ambient temperature (c) power supply rejection ratio (db) 1 10 100 1,000 50 75 100 125 ambient temperature (c) input bias current (pa) v dd = 5.5v ch0 = 5.0v mcp6s92/3 mcp6s91 1.e-13 1.e-12 1.e-11 1.e-10 1.e-09 1.e-08 1.e-07 -50 -25 0 25 50 75 100 125 ambient temperature (c) quiescent current in shutdown (a) in shutdown mode ch0 = v dd /2 v dd = 2.5v v dd = 5.5v 100n 10n 1n 100p 10p 1p 100f 20 30 40 50 60 70 80 90 100 1 0 10 0 1000 1000 0 10 0000 10 00000 frequency (hz) power supply rejection ratio (db) v dd = 5.5v v dd = 2.5v 1k 10k 1m 10 100 input referred 100k 1 10 100 1,000 10,000 0.00.51.01.52.02.53.03.54.04.55.05.5 input voltage (v) input bias current (pa) t a = +85c mcp6s92/3 v dd = 5.5v t a = +125c 0% 5% 10% 15% 20% 25% 1014 18 22 26 30 34 38 42 quiescent current in shutdown (pa) percentage of occurrences 39 samples v dd = 5.5v ch0 = v dd /2 downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 13 mcp6s91/2/3 note: unless otherwise indicated, t a = +25c, v dd = +2.5v to +5.5v, v ss = gnd, v ref =v ss , g = +1 v/v, input = ch0 = (0.3v)/g, ch1 = 0.3v, r l =10k to v dd /2 and c l = 60 pf. figure 2-19: quiescent current vs. supply voltage. figure 2-20: dc output non-linearity vs. supply voltage. figure 2-21: output voltage headroom vs. output plus ladder current (circuit in figure 4-2). figure 2-22: output short circuit current vs. supply voltage. figure 2-23: dc output non-linearity vs. output swing. figure 2-24: output voltage swing vs. frequency. 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0.00.51.01.52.02.53.03.54.04.55.05.5 supply voltage (v) quiescent current (ma) t a = +125c t a = +85c t a = +25c t a = -40c 0.001 0.01 0.1 1 2.53.03.54.04.55.05.5 power supply voltage (v) dc output non-linearity, input referred (% of fsr) v out = 0.3v to v dd - 0.3v v onl /g, g = +1 g = +2 g +4 1 10 100 1000 0.1 1 10 output plus ladder current magnitude (ma) output voltage headroom; v dd -v oh and v ol -v ss (mv) v dd = 5.5v v dd = 2.5v 0 5 10 15 20 25 30 35 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 power supply voltage (v) output short circuit current magnitude (ma) t a = +125c t a = +85c t a = +25c t a = -40c 0.001 0.01 0.1 1 11 0 output voltage swing (v p-p ) dc output non-linearity, input referred (% of fsr) v dd = 5.5v v onl /g: g = +1 g = +2 g +4 0.1 1 10 1.e+05 1.e+06 1.e+07 frequency (hz) output voltage swing (v p-p ) 100k 10m 1m v dd = 5.5v v dd = 2.5v g = 1, 2 g = 4 to 10 g = 16, 32 downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 14 mcp6s91/2/3 note: unless otherwise indicated, t a = +25c, v dd = +2.5v to +5.5v, v ss = gnd, v ref =v ss , g = +1 v/v, input = ch0 = (0.3v)/g, ch1 = 0.3v, r l =10k to v dd /2 and c l = 60 pf. figure 2-25: gain vs. frequency. figure 2-26: bandwidth vs. capacitive load. figure 2-27: thd plus noise vs. frequency, v out =2v p-p . figure 2-28: gain peaking vs. capacitive load. figure 2-29: the mcp6s91/2/3 family shows no phase reversal under overdrive. figure 2-30: thd plus noise vs. frequency, v out =4v p-p . -20 -10 0 10 20 30 40 1.e+0 5 1.e+06 1.e+07 1.e+08 frequency (hz) gain (db) g = +2 g = +1 1m 10m 100m 100k g = +32 g = +16 g = +10 g = +8 g = +5 g = +4 1 10 100 10 100 1000 capacitive load (pf) bandwidth (mhz) g = +1g = +4 g = +16 0.0001 0.001 0.01 0.1 1 1.e+02 1.e+0 3 1.e+0 4 1.e+05 frequency (hz) thd + noise (%) 100 1k 100k 10k g = +1, r l = 10 k to 1.5v g = +4 g = +1 g = +16 measurement bw = 80 khz v out = 2.0v p-p v dd = 5.0v 0 1 2 3 4 5 6 7 10 100 1000 capacitive load (pf) gain peaking (db) g = +16 g = +4 g = +1 -1 0 1 2 3 4 5 6 012 34567 8910 time (1 s/div) input, output voltage (v) v dd = 5.0v g = +1 v/v v in v out 0.0001 0.001 0.01 0.1 1 1.e+02 1.e+03 1.e+0 4 1.e+0 5 frequency (hz) thd + noise (%) measurement bw = 80 khz v out = 4 v p-p v dd = 5.0v 100 1k 100k 10k g = +4 g = +1 g = +16 downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 15 mcp6s91/2/3 note: unless otherwise indicated, t a = +25c, v dd = +2.5v to +5.5v, v ss = gnd, v ref =v ss , g = +1 v/v, input = ch0 = (0.3v)/g, ch1 = 0.3v, r l =10k to v dd /2 and c l = 60 pf. figure 2-31: small-signal pulse response. figure 2-32: channel select timing. figure 2-33: output voltage vs. shutdown mode. figure 2-34: large-signal pulse response. figure 2-35: gain select timing. figure 2-36: minimum valid supply voltage (register data still valid). -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 0 .00 0 0.200 0 .40 0 0.600 0.8 00 1.000 1.2 00 1.400 1.600 1 .80 0 2.000 time (200 ns/div) output voltage (10 mv/div) -300 -250 -200 -150 -100 -50 0 50 100 150 200 250 300 normalized input voltage (50 mv/div) v dd = 5.0v v out g = +1 g = +5 g = +32 gv in 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0 .00 0.50 1.00 1.5 0 2.0 0 2.50 3.00 3.50 4 .0 0 4 .50 5.00 time (500 ns/div) output voltage (v) -20 -15 -10 -5 0 5 10 15 20 chip select voltage (v) 50 v out (ch0 = 0.6v, g = +1) v out (ch1 = 0.3v, g = +1) cs cs 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.e+0 0 1.e+00 2.e+0 0 3.e+00 4 .e+00 5.e+00 6 .e+00 7.e+0 0 8 .e+00 9.e+0 0 1.e+01 1.e+0 1 1.e+01 time (1 s/div) output voltage (mv) -15 -10 -5 0 5 10 15 chip select voltage (v) v out is "on" shutdown cs cs shutdown v dd = 5.0v ch0 = 0.3v g = +1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 time (500 ns/div) output voltage (v) -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 normalized input voltage (1v/div) v dd = 5.0v gv in v out g = +1 g = +5 g = +32 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 5 00 1 000 1500 2000 2500 3 000 3 500 4 000 45 00 50 00 time (500 ns/div) output voltage (v) -20 -15 -10 -5 0 5 10 15 20 chip select voltage (v) v out (ch0 = 0.3v, g = +5) v out (ch0 = 0.3v, g = +1) cs cs 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 0.00.5 1.0 1.5 2.0 minimum valid supply voltage (v) percentage of occurrences 32 samples 1 st wafer lot downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 16 mcp6s91/2/3 note: unless otherwise indicated, t a = +25c, v dd = +2.5v to +5.5v, v ss = gnd, v ref =v ss , g = +1 v/v, input = ch0 = (0.3v)/g, ch1 = 0.3v, r l =10k to v dd /2 and c l = 60 pf. figure 2-37: input offset voltage vs. input voltage, v dd = 2.5v. figure 2-38: output voltage headroom vs. ambient temperature. figure 2-39: input offset voltage vs. input voltage, v dd = 5.5v. 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0.0 0.5 1.0 1.5 2.0 2.5 input voltage (v) input offset voltage (mv) g = 1 v/v v dd = 2.5v t a = +125c t a = +85c t a = +25c t a = -40c 0 5 10 15 20 25 30 35 -50 -25 0 25 50 75 100 125 ambient temperature (c) output voltage headroom; v dd Cv oh and v ol Cv ss (mv) v dd = 5.5v: v dd Cv oh v ol Cv ss v dd = 2.5v: v dd Cv oh v ol Cv ss v ref = v ss 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 input voltage (v) input offset voltage (mv) g = 1 v/v v dd = 5.5v t a = +125c t a = +85c t a = +25c t a = -40c downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 17 mcp6s91/2/3 3.0 pin descriptions descriptions of the pins are listed in table 3-1. table 3-1: pin function table 3.1 analog output the output pin (v out ) is a low-impedance voltage source. the selected gain (g), selected input (ch0, ch1) and voltage at v ref determine its value. 3.2 analog inputs (ch0, ch1) the inputs ch0 and ch1 connect to the signal sources. they are high-impedance cmos inputs with low bias currents. the internal mux selects which one is amplified to the output. 3.3 external reference voltage (v ref ) the v ref pin, which is an analog input, should be at a voltage between v ss and v dd (the mcp6s92 has v ref tied internally to v ss ). the voltage at this pin shifts the output voltage. 3.4 power supply (v ss and v dd ) the positive power supply pin (v dd ) is 2.5v to 5.5v higher than the negative power supply pin (v ss ). for normal operation, the other pins are at voltages between v ss and v dd . typically, these parts are used in a single (positive) supply configuration. in this case, v ss is connected to ground and v dd is connected to the supply. v dd will need a local bypass capacitor (typically 0.01 f to 0.1 f) within 2 mm of the v dd pin. these parts can share a bulk capacitor with analog parts (typically 2.2 f to 10 f) within 100 mm of the v dd pin. 3.5 digital inputs the spi interface inputs are: chip select (cs ), serial input (si) and serial clock (sck). these are schmitt- triggered, cmos logic inputs. 3.6 digital output the mcp6s93 device has a spi interface serial output (so) pin. this is a cmos push-pull output and does not ever go high-z. once the device is deselected (cs goes high), so is forced low. this feature supports daisy-chaining, as explained in section 5.3 daisy- chain configuration . mcp6s91 mcp6s92 mcp6s93 symbol description 111v out analog output 2 2 2 ch0 analog input 3 3 ch1 analog input 34v ref external reference pin 445v ss negative power supply 556 cs spi? chip select 6 6 7 si spi serial data input 8 so spi serial data output 7 7 9 sck spi clock input 881 0v dd positive power supply downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 18 mcp6s91/2/3 4.0 analog functions the mcp6s91/2/3 family of programmable gain amplifiers (pga) is based on simple analog building blocks (see figure 4-1). each of these blocks will be explained in more detail in the following subsections. figure 4-1: pga block diagram. 4.1 input mux the mcp6s91 has one input, while the mcp6s92 and mcp6s93 have two inputs (see figure 4-1). for the lowest input current, float unused inputs. tying these pins to a voltage near the active channels bias voltage also works well. for simplicity, they can be tied to v ss or v dd , but the input current may increase. the one-channel mcp6s91 has approximately the same input bias current as the two-channel mcp6s92 and mcp6s93. the input offset voltage mismatch between channels ( ? v os ) is, ideally, 0 v. the input mux uses cmos transmission gates that have drain-source (channel) resistance, but no offset voltage. the histogram in figure 2-8 reflects the measurement repeatability (i.e., noise power bandwidth) rather than the actual mismatch. reducing the measurement bandwidth will produce a more narrow histogram and give an aver- age closer to 0 v. 4.2 internal op amp the internal op amp gives the right combination of bandwidth, accuracy and flexibility. 4.2.1 compensation capacitors the internal op amp has three compensation capaci- tors (comp. caps.) connected to a switching network. they are selected to give good small-signal bandwidth at high gains and good slew rates (full-power band- width) at low gains. the change in bandwidth as gain changes is between 2 and 12 mhz. refer to table 4-1 for more information. table 4-1: gain vs. internal compensation capacitor 4.2.2 rail-to-rail channel inputs the input stage of the internal op amp uses two differ- ential input stages in parallel; one operates at low v in (input voltage), while the other operates at high v in . with this topology, the internal inputs can operate to 0.3v past either supply rail. the input offset voltage is measured at both v in =v ss C 0.3v and v dd + 0.3v to ensure proper operation. the transition between the two input stages occurs when v in v dd C 1.5v. for the best distortion and gain linearity, avoid this region of operation. mcp6s91 C one input (ch0), no so pin mcp6s92 C two inputs (ch0, ch1), v ref tied internally to v ss , no so pin mcp6s93 C two inputs (ch0, ch1) v out v ref v dd cs si so sck ch1 ch0 v ss 8 r f r g mux spi? logic gain switches resistor ladder (r lad ) gain (v/v) internal comp. cap. gbwp (mhz) typ. sr (v/s) typ. fpbw (mhz) typ. bw (mhz) typ. 1 large 12 4.0 0.30 12 2 large 12 4.0 0.30 6 4m e d i u m 2 0 1 1 0 . 7 0 1 0 5m e d i u m 2 0 1 1 0 . 7 0 7 8 medium 20 11 0.70 2.4 10 medium 20 11 0.70 2.0 16 small 64 22 1.6 5 32 small 64 22 1.6 2.0 note 1: fpbw is the full-power bandwidth. these numbers are based on v dd =5.0v. 2: no changes in dc performance (e.g., v os ) accompany a change in compensation capacitor. 3: bw is the closed-loop, small signal -3 db bandwidth. downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 19 mcp6s91/2/3 4.2.3 rail-to-rail output the maximum output voltage swing is the maximum swing possible under a particular amplifier load current. the amplifier load current is the sum of the external load current (i out ) and the current through the ladder resistance (i lad ); see figure 4-2. equation 4-1: figure 4-2: amplifier load current. see figure 2-21 for the typical output headroom (v dd C v oh or v ol C v ss ) as a function of amplifier load current. the specification table states the output can reach within 60 mv of either supply rail when r l =10k and v ref =v dd /2. 4.2.4 input voltage and phase reversal the mcp6s91/2/3 amplifier family is designed with cmos input devices. it is designed to not exhibit phase inversion when the input pins exceed the supply voltages. figure 2-29 shows an input voltage exceeding both supplies with no resulting phase inversion. the maximum voltage that can be applied to the input pins (chx) is v ss C0.3v to v dd + 0.3v. voltages on the inputs that exceed this absolute maximum rating can cause excessive current to flow into or out of the input pins. current beyond 2 ma can cause possible reliability problems. applications that exceed this rating must be externally limited with an input resistor, as shown in figure 4-3. figure 4-3: r in limits the current flow into an input pin. 4.3 resistor ladder the resistor ladder shown in figure 4-1 (r lad =r f +r g ) sets the gain. placing the gain switches in series with the inverting input reduces the parasitic capacitance, distortion and gain mismatch. r lad is an additional load on the output of the pga and causes additional current draw from the supplies. it is also a load (z in_ref ) on the external circuitry driving the v ref pin. in shutdown mode, r lad is still attached to the v out and v ref pins. thus, these pins and the internal ampli- fiers inverting input are all connected through r lad and the output is not high-z (unlike the internal op amp). while r lad contributes to the output noise, its effect is small. refer to figure 2-12. where: amplifier load current i out i lad + = i lad v out v ref C () r lad ------------------------------------- = v out v ref r lad i out i lad mcp6s9x chx r in v in r in v ss C (maximum expected v in ) 2 ma r in (maximum expected v in ) C v dd 2 ma v out downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 20 mcp6s91/2/3 4.4 rail-to-rail v ref input the v ref input is intended to be driven by a low- impedance voltage source. the source driving the v ref pin should have an output impedance less than 0.1 to maintain reasonable gain accuracy. the supply voltage v ss and v dd usually meet this requirement. r lad presents a load at the v ref pin to the external circuit (z in_ref (5 k /g)||(6 pf)), which depends on the gain. any source driving the v ref pin must be capable of driving a load as heavy as 0.16 k ||6 pf (g = 32). the absolute maximum voltages that can be applied to the reference input pin (v ref ) are v ss C0.3v and v dd + 0.3v. voltages on the inputs that exceed this absolute maximum rating can cause excessive current to flow into or out of this pin. current beyond 2 ma can cause possible reliability problems. because an external series resistor cannot be used (for low gain error), the external circuit must ensure that v ref is between v ss C 0.3v and v dd +0.3v. the v ivr_ref spec shows the region of normal operation for the v ref pin (v ss to v dd ). staying within this region ensures proper operation of the pga and its surrounding circuitry. 4.5 shutdown mode these pgas use a software shutdown command. when the spi interface sends a shutdown command, the internal op amp is shut down and its output placed in a high-z state. the resistive ladder is always connected between v ref and v out ; even in shutdown. this means that the output resistance will be on the order of 5 k , with a path for output signals to appear at the input. downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 21 mcp6s91/2/3 5.0 digital functions the mcp6s91/2/3 pgas use a standard spi compatible serial interface to receive instructions from a controller. this interface is configured to allow daisy- chaining with other spi devices. 5.1 spi timing chip select (cs ) toggles low to initiate communica- tion with these devices. the first byte of each si word (two bytes long) is the instruction byte, which goes into the instruction register. the instruction register points the second byte to its destination. in a typical application, cs is raised after one word (16 bits) to implement the desired changes. section 5.3 daisy- chain configuration , covers applications using multiple 16-bit words. so goes low after cs goes high; it has a push-pull output that does not go into a high-z state. the mcp6s91/2/3 devices operate in spi modes 0,0 and 1,1. in 0,0 mode, the clock idles in the low state (figure 5-1). in 1,1 mode, the clock idles in the high state (figure 5-2). in both modes, si data is loaded into the pga on the rising edge of sck, while so data is clocked out on the falling edge of sck. in 0,0 mode, the falling edge of cs also acts as the first falling edge of sck (see figure 5-1). there must be multiples of 16 clocks (sck) while cs is low or commands will abort (see section 5.3 daisy-chain configuration ). figure 5-1: serial bus sequence for the pga; spi? 0,0 mode (see figure 1-4). figure 5-2: serial bus sequence for the pga; spi? 1,1 mode (see figure 1-5). 123456789 10 11 12 13 14 15 16 bit 7 cs sck si instruction byte data byte bit 0 bit 7 bit 0 so (first 16 bits out are always zeros) 123456789 10 11 12 13 14 15 16 bit 7 cs sck si instruction byte data byte bit 0 bit 7 bit 0 so (first 16 bits out are always zeros) downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 22 mcp6s91/2/3 5.2 registers the analog functions are programmed through the spi interface using 16-bit words (see figure 5-1 and figure 5-2). this data is sent to two of three 8-bit regis- ters: instruction register (register 5-1), gain register (register 5-2) and channel register (register 5-3). there are no power-up defaults for these three registers. 5.2.1 ensuring valid data in the registers after power up, the registers contain random data that must be initialized. sending valid gain and channel selection commands to the internal registers puts valid data into those registers. also, the internal state machine starts in an arbitrary state. toggling the chip select pin (cs ) from high to low, then back to high again, puts the internal state machine in a known, valid condition (this can be done by entering any valid command). after power-up, and when the power supply voltage dips below the minimum valid v dd (v dd_val ), the inter- nal register data and state machine may need to be reset. this is accomplished as described before. use an external system supervisor to detect these events so that the microcontroller will reset the pga state and registers. a 0.1 f bypass capacitor mounted as close as possible to the v dd pin provides additional transient immunity. 5.2.2 instruction register the instruction register has 3 command bits and 1 indi- rect address bit; see register 5-1. the command bits include a nop ( 000 ) to support daisy-chaining (see section 5.3 daisy-chain configuration ); the other nop commands shown should not be used (they are reserved for future use). the device is brought out of shutdown mode when a valid command, other than nop or shutdown, is sent and cs is raised. register 5-1: instruction register w-0 w-0 w-0 u-x u-x u-x u-x w-0 m2 m1 m0 a 0 bit 7 bit 0 bit 7-5 m2-m0: command bits 000 = nop (note 1) 001 = pga enters shutdown mode as soon as a full 16-bit word is sent and cs is raised. (notes 1 and 2) 010 = write to register. 011 = nop (reserved for future use) (note 1) 1xx = nop (reserved for future use) (note 1) bit 4-1 unimplemented: read as 0 (reserved for future use) bit 0 a0: indirect address bit 1 = addresses the channel register 0 = addresses the gain register note 1: all other bits in the 16-bit word (including a0) are dont cares. 2: the device exits shutdown mode when a valid command (other than nop or shutdown) is sent and cs is raised; that valid command will be executed. shutdown does not toggle. legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 23 mcp6s91/2/3 5.2.3 setting the gain the amplifier can be programmed to produce binary and decimal gain settings between +1 v/v and +32 v/v. register 5-2 shows the details. at the same time, differ- ent compensation capacitors are selected to optimize the bandwidth vs. slew rate trade-off (see table 4-1). register 5-2: gain register u-x u-x u-x u-x u-x w-0 w-0 w-0 g 2g 1g 0 bit 7 bit 0 bit 7-3 unimplemented: read as 0 (reserved for future use) bit 2-0 g2-g0: gain select bits 000 = gain of +1 001 = gain of +2 010 = gain of +4 011 = gain of +5 100 = gain of +8 101 = gain of +10 110 = gain of +16 111 = gain of +32 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 24 mcp6s91/2/3 5.2.4 changing the channel if the instruction register is programmed to address the channel register, the multiplexed inputs of the mcp6s92 and mcp6s93 can be changed using register 5-3. register 5-3: channel register u-x u-x u-x u-x u-x u-x u-x w-0 c 0 bit 7 bit 0 bit 7-1 unimplemented: read as 0 (reserved for future use) bit 0 c0: channel select bit 0 = 1 = mcp6s91 ch0 ch0 mcp6s92 ch0 ch1 mcp6s93 ch0 ch1 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 25 mcp6s91/2/3 5.2.5 shutdown command the software shutdown command allows the user to put the amplifier into a low-power mode (see register 5-1). in this shutdown mode, most pins are high-impedance ( section 4.5 shutdown mode and section 5.1 spi timing cover the exceptions at pins v ref, v out and so). once the pga has entered shutdown mode, it will remain in this mode until either a valid command is sent to the device (other than nop or shutdown) or the device is powered down and back up again. the internal registers maintain their values while in shutdown. once brought out of shutdown mode, the part returns to its previous state (see section 5.2.1 ensuring valid data in the registers for exceptions to this rule). this makes it possible to bring the device out of shutdown mode using one command; send a com- mand to select the current channel (or gain) and the device will exit shutdown with the same state that existed before shutdown. 5.3 daisy-chain configuration multiple mcp6s91/2/3 devices can be connected in a daisy-chain configuration by connecting the so pin from one device to the si pin on the next device and using common sck and cs lines (figure 5-3). this approach reduces pcb layout complexity and uses fewer picmicro ? microcontroller i/o pins. the example in figure 5-3 shows a daisy-chain configuration with two devices, although any number of devices can be configured this way. the mcp6s91 and mcp6s92 can only be used at the far end of the daisy- chain, because they do not have a serial data out (so) pin. as shown in figure 5-4 and figure 5-5, both si and so data are sent in 16-bit (2 byte) words. these devices abort any command that is not a multiple of 16 bits. when using the daisy-chain configuration, the maxi- mum clock speed possible is reduced to 5.8 mhz due to the so pins propagation delay (see electrical specifications). the internal spi shift register is automatically loaded with zeros whenever cs goes high (a command is executed). thus, the first 16-bits out of the so pin after the cs line goes low are always zeros. this means that the first command loaded into the next device in the daisy-chain is a nop . this feature makes it possible to send shorter command and data byte strings when the farthest devices do not need to change. for example, if there were three devices on the chain, and only the middle device needed changing, then only 32 bytes of data need to be transmitted (for the first and middle devices). the last device on the chain would receive a nop when the cs pin is raised to execute the command. figure 5-3: daisy-chain configuration. picmicro ? so cs scksi cs sck so device 1 device 1 00100000 00000000 so cs sck si device 2 device 2 00000000 00000000 device 1 01000001 00000111 device 2 00100000 00000000 4. clock out the instruction and data for device 1 (16 clocks) to device 1. 5. device 1 automatically shifts data from device 1 to device 2 (16 clocks). 6. raise cs . 1. set cs low. 2. clock out the instruction and data for device 2 (16 clocks) to device 1. 3. device 1 automatically clocks out all zeros (first 16 clocks) to device 2. microcontroller downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 26 mcp6s91/2/3 figure 5-4: serial bus sequence for daisy-chain configuration; spi? 0,0 mode. figure 5-5: serial bus sequence for daisy-chain configuration; spi? 1,1 mode. 1234567891011121314 1516 bit 7 cs sck si instruction byte data byte bit 0 bit 7 bit 0 so (first 16 bits out are always zeros) 1234567891011 1213141516 bit 7 instruction byte data byte bit 0 bit 7 bit 0 for device 2 for device 2 for device 1 for device 1 bit 7 instruction byte data byte bit 0 bit 7 bit 0 for device 2 for device 2 1234567891011 1213141516 bit 7 cs sck si instruction byte data byte bit 0 bit 7 bit 0 so (first 16 bits out are always zeros) 1 2 3 4 5 6 7 8 9 10111213141516 bit 7 instruction byte data byte bit 0 bit 7 bit 0 for device 2 for device 2 for device 1 for device 1 bit 7 instruction byte data byte bit 0 bit 7 bit 0 for device 2 for device 2 downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 27 mcp6s91/2/3 6.0 applications information 6.1 changing external reference voltage figure 6-1 shows a mcp6s91 with the v ref pin at 2.5v and v dd = 5.0v. this allows the pga to amplify signals centered on 2.5v, instead of ground-referenced signals. the voltage reference mcp1525 is buffered by a mcp6021, which gives a low output impedance reference voltage from dc to high frequencies. the source driving the v ref pin should have an output impedance less than 0.1 to maintain reasonable gain accuracy. figure 6-1: pga with different external reference voltage. 6.2 capacitive load and stability large capacitive loads can cause stability problems and reduced bandwidth for the mcp6s91/2/3 family of pgas (figure 2-26 and figure 2-28). as the load capacitance increases, there is a corresponding increase in frequency response peaking and step response overshoot and ringing. this happens because a large load capacitance decreases the internal amplifiers phase margin and bandwidth. when driving large capacitive loads with these pgas (i.e., > 60 pf), a small series resistor at the output (r iso in figure 6-2) improves the internal amplifiers stability by making the load resistive at higher frequencies. the bandwidth will be generally lower than the bandwidth with no capacitive load. figure 6-2: pga circuit for large capacitive loads. figure 6-3 gives recommended r iso values for different capacitive loads. after selecting r iso for your circuit, double-check the resulting frequency response peaking and step response overshoot on the bench. modify r iso s value until the response is reasonable at all gains. figure 6-3: recommended r iso . 6.3 layout considerations good pc board layout techniques will help achieve the performance shown in the electrical characteristics and typical performance curves. it will also help minimize electromagnetic compatibility (emc) issues. 6.3.1 component placement separate different circuit functions: digital from analog, low-speed from high-speed, and low-power from high- power. this will reduce crosstalk. keep sensitive traces short and straight. separate them from interfering components and traces. this is especially important for high-frequency (low rise time) signals. v dd v dd v dd v ref v in v out mcp1525 mcp6021 1f mcp6s91 2.5v ref v in v out mcp6s9x r iso c l 10 100 1,000 10 100 1,000 10,000 l oad c apacitance (f) r ecommended r iso ( ) 10 p 100 p 1 n 10 n downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 28 mcp6s91/2/3 6.3.2 supply bypass use a local bypass capacitor (0.01 f to 0.1 f) within 2mm of the v dd pin. it must connect directly to the ground plane. a multi-layer ceramic chip capacitor, or high-frequency equivalent, works best. use a bulk bypass capacitor (2.2 f to 10 f) within 100 mm of the v dd pin. it needs to connect to the ground plane. a multi-layer ceramic chip capacitor, tantalum or high-frequency equivalent, works best. this capacitor may be shared with other nearby analog parts. 6.3.3 input source impedance the sources driving the inputs of the pgas need to have reasonably low source impedance at higher frequencies. figure 6-4 shows how the external source impedance (r s ), pga package pin capacitance (c p1 ) and pga package pin-to-pin capacitance (c p2 ) form a positive feedback voltage divider network. feedback to the selected channel may cause frequency response peaking and step response overshoot and ringing. feedback to an unselected channel will produce crosstalk. figure 6-4: positive feedback path. figure 2-6 shows the crosstalk (referred to input) that results when a hostile signal is connected to ch1, input ch0 is selected and r s is connected from ch0 to gnd. a gain of +32 was chosen for this plot because it demonstrates the worst-case behavior. increasing r s increases the crosstalk as expected. at a source impedance of 10 k , there is noticeable peaking in the response; this is due to positive feedback. most designs should use a source resistance (r s ) no larger than 10 k . careful attention to layout parasitics and proper component selection will help minimize this effect. when a source impedance larger than 10 k must be used, place a capacitor in parallel to c p1 to reduce the positive feedback. this capacitor needs to be large enough to overcome gain (or crosstalk) peak- ing, yet small enough to allow a reasonable signal bandwidth. 6.3.4 signal coupling the input pins of the mcp6s91/2/3 family of pgas are high-impedance. this makes them especially suscepti- ble to capacitively-coupled noise. using a ground plane helps reduce this problem. when noise is capacitively coupled, the ground plane provides additional shunt capacitance to ground. when noise is magnetically coupled, the ground plane reduces the mutual inductance between traces. increasing the separation between traces makes a significant difference. changing the direction of one of the traces can also reduce magnetic coupling. it may help to locate guard traces next to the victim trace. they should be on both sides of, and as close as possible to, the victim trace. connect the guard traces to the ground plane at both ends. also connect long guard traces to the ground plane in the middle. 6.3.5 high-frequency issues because the mcp6s91/2/3 pgas frequency response reaches unity gain at 64 mhz when g = 16 and 32, it is important to use good pcb layout techniques. any parasitic-coupling at high-frequency might cause undesired peaking. filtering high-frequency signals (i.e., fast edge rates) can help. to minimize high- frequency problems: ? use complete ground and power planes ? use hf, surface-mount components ? provide clean supply voltages and bypassing ? keep traces short and straight ? try a linear power supply (e.g., a ldo) v in mcp6s9x v out r s c p1 c p2 downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 29 mcp6s91/2/3 6.4 typical applications 6.4.1 gain ranging figure 6-5 shows a circuit that measures the current i x . the circuits performance benefits from changing the gain on the pga. just as a hand-held multimeter uses different measurement ranges to obtain the best results, this circuit makes it easy to set a high gain for small signals and a low gain for large signals. as a result, the required dynamic range at the pgas output is less than at its input (by up to 30 db). figure 6-5: wide dynamic range current measurement circuit. 6.4.2 shifted gain range pga figure 6-6 shows a circuit using a mcp6291 at a gain of +10 in front of a mcp6s91. this shifts the overall gain range to +10 v/v to +320 v/v (from +1 v/v to +32 v/v). figure 6-6: pga with higher gain range. it is also easy to shift the gain range to lower gains (see figure 6-7). the mcp6291 acts as a unity gain buffer, and the resistive voltage divider shifts the gain range down to +0.1 v/v to +3.2 v/v (from +1 v/v to +32 v/v). figure 6-7: pga with lower gain range. 6.4.3 extended gain range pga figure 6-8 gives a +1 v/v to +1024 v/v gain range, which is much greater than the range for a single pga (+1 v/v to +32 v/v). the first pga provides input multiplexing capability, while the second pga only needs one input. these devices can be daisy-chained ( section 5.3 daisy-chain configuration ). figure 6-8: pga with extended gain range. 6.4.4 multiple sensor amplifier the multiple-channel pgas (mcp6s92 and mcp6s93) allow the user to select which sensor appears on the output (see figure 6-9). these devices can also change the gain to optimize performance for each sensor. figure 6-9: pga with multiple sensor inputs. i x v out mcp6s9x r s v in v out mcp6291 mcp6s91 1.11 k 10.0 k v in mcp6291 1.11 k 10.0 k v out mcp6s91 v in v out mcp6s92 mcp6s91 sensor # 0 v out mcp6s93 sensor # 1 downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 30 mcp6s91/2/3 6.4.5 expanded input pga figure 6-10 shows cascaded mcp6s28 and mcp6s92s pgas that provide up to 9 input channels. obviously, sensors #1-8 have a high total gain range available, as explained in section 6.4.3 extended gain range pga . these devices can be daisy- chained ( section 5.3 daisy-chain configuration ). figure 6-10: pga with expanded inputs. 6.4.6 picmicro ? mcu with expanded input capability figure 6-11 shows a mcp6s93 driving an analog input to a picmicro microcontroller. this greatly expands the input capacity of the microcontroller, while adding the ability to select the appropriate gain for each source. figure 6-11: expanded input for a picmicro ? microcontroller. 6.4.7 adc driver this family of pgas is well suited for driving analog-to- digital converters (adcs). the binary gains (1, 2, 4, 8, 16 and 32) effectively add five more bits to the input range (see figure 6-12). this works well for applica- tions needing relative accuracy more than absolute accuracy (e.g., power monitoring). figure 6-12: pga as an adc driver. at low gains, the adcs signal-to-noise ratio (snr) will dominate since the pgas input noise voltage density is so low (10 nv/ hz @ 10 khz, typ.). at high gains, the pgas noise will dominate the snr, but it is low enough to support most applications. these pgas add the flexibility of selecting the best gain for an application. the low-pass filter in the block diagram reduces the integrated noise at the mcp6s92s output and serves as an anti-aliasing filter. this filter may be designed using microchips filterlab ? software, available at www.microchip.com. sensor v out mcp6s92 # 0 sensors mcp6s28 # 1-8 v in spi ? mcp6s93 picmicro ? microcontroller out mcp3201 12-bit adc 3 mcp6s92 v in low-pass filter downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 31 mcp6s91/2/3 7.0 packaging information 7.1 package marking information xxxxxxxxxxxxxnnn yyww 8-lead pdip (300 mil) ( mcp6s91 , mcp6s92 ) example: 8-lead soic (150 mil) ( mcp6s91 , mcp6s92 ) example: xxxxxxxxxxxxyyww nnn mcp6s91e/p256 0424 mcp6s91 e/sn0424 256 8-lead msop ( mcp6s91, mcp6s92 ) example: xxxxx ywwnnn 6s91e 424256 legend: xx...x customer specific information* yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * standard marking consists of microchip part number, year code, week code, traceability code (facil ity code, mask rev#, and assembly code). for marking beyond this, certain price adders apply. please check with your microchip sales office. 10-lead msop ( mcp6s93 ) example: xxxxx ywwnnn 6s93e 424256 downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 32 mcp6s91/2/3 8-lead plastic dual in-line (p) C 300 mil (pdip) b1 b a1 a l a2 p e eb c e1 n d 1 2 units inches* millimeters dimension limits min nom max min nom max number of pins n 88 pitch p .100 2.54 top to seating plane a .140 .155 .170 3.56 3.94 4.32 molded package thickness a2 .115 .130 .145 2.92 3.30 3.68 base to seating plane a1 .015 0.38 shoulder to shoulder width e .300 .313 .325 7.62 7.94 8.26 molded package width e1 .240 .250 .260 6.10 6.35 6.60 overall length d .360 .373 .385 9.14 9.46 9.78 tip to seating plane l .125 .130 .135 3.18 3.30 3.43 lead thickness c .008 .012 .015 0.20 0.29 0.38 upper lead width b1 .045 .058 .070 1.14 1.46 1.78 lower lead width b .014 .018 .022 0.36 0.46 0.56 overall row spacing eb .310 .370 .430 7.87 9.40 10.92 mold draft angle top 51 01 5 51 01 5 mold draft angle bottom 51 01 5 51 01 5 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed jedec equivalent: ms-001 drawing no. c04-018 .010 (0.254mm) per side. significant characteristic downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 33 mcp6s91/2/3 8-lead plastic small outline (sn) C narrow, 150 mil (soic) foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.33 .020 .017 .013 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 0.76 0.62 0.48 .030 .025 .019 l foot length 0.51 0.38 0.25 .020 .015 .010 h chamfer distance 5.00 4.90 4.80 .197 .193 .189 d overall length 3.99 3.91 3.71 .157 .154 .146 e1 molded package width 6.20 6.02 5.79 .244 .237 .228 e overall width 0.25 0.18 0.10 .010 .007 .004 a1 standoff 1.55 1.42 1.32 .061 .056 .052 a2 molded package thickness 1.75 1.55 1.35 .069 .061 .053 a overall height 1.27 .050 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n p b e e1 h l c 45 a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 (0.254mm) per side. jedec equivalent: ms-012 drawing no. c04-057 significant characteristic downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 34 mcp6s91/2/3 8-lead plastic micro small outline package (ms) (msop) p a a1 a2 d l c dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not .037 .035 f footprint (reference) exceed .010" (0.254mm) per side. notes: drawing no. c04-111 *controlling parameter mold draft angle top mold draft angle bottom foot angle lead width lead thickness c b 77 .004 .010 0 .006 .012 (f) dimension limits overall height molded package thickness molded package width overall length foot length standoff overall width number of pins pitch a l e1 d a1 e a2 .016 .114 .114 .022 .118 .118 .002 .030 .193 .034 min p n units .026 nom 8 inches 1.00 0.95 0.90 .039 0.15 0.30 .008 .016 6 0.10 0.25 0 77 0.20 0.40 6 millimeters* 0.65 0.86 3.00 3.00 0.55 4.90 .044 .122 .028 .122 .038 .006 0.40 2.90 2.90 0.05 0.76 min max nom 1.18 0.70 3.10 3.10 0.15 0.97 max 8 e1 e b n 1 2 significant characteristic .184 .200 4.67 .5.08 downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 35 mcp6s91/2/3 10-lead plastic micro small outline package (ms) (msop) dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not .037 ref f footprint exceed .010" (0.254mm) per side. notes: drawing no. c04-021 *controlling parameter mold draft angle topmold draft angle bottom foot anglelead width lead thickness c b .003.006 - .009 dimension limits overall heightmolded package thickness molded package width overall length foot length standoffoverall width number of pinspitch a l e1 d a1 e a2 .016 .024 .118 bsc.118 bsc .000 .030 .193 bsc .033 min p n units .020 typ nom 10 inches 0.95 ref - 0.23 .009 .012 0.080.15 -- 0.230.30 millimeters* 0.50 typ. 0.85 3.00 bsc3.00 bsc 0.60 4.90 bsc .043 .031 .037.006 0.40 0.00 0.75 min max nom 1.10 0.80 0.15 0.95 max 10 5 15 5 15 - -- 0 - 8 5 - 5 - 15 15 jedec equivalent: mo-187 8 0 e l d (f) b p e1 n a2 1 2 c a1 a l1 - - -- downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 36 mcp6s91/2/3 notes: downloaded from: http:///
? 2004 microchip technology inc. ds21908a-page 37 mcp6s91/2/3 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . sales and support device: mcp6s91: one-channel pga mcp6s91t: one-channel pga (tape and reel for soic and msop-8) mcp6s92: two-channel pga mcp6s92t: two-channel pga (tape and reel for soic and msop-8) mcp6s93: two-channel pga mcp6s93t: two-channel pga (tape and reel for msop-10) temperature range: e = -40c to +125c package: ms = plastic micro small outline (msop), 8-lead p = plastic dip (300 mil body), 8-lead sn = plastic soic (150 mil body), 8-lead un = plastic micro small outline (msop), 10-lead examples: a) mcp6s91-e/p: one-channel pga, pdip package. b) mcp6s91-e/sn: one-channel pga, soic package. c) mcp6s91-e/ms: one-channel pga, msop package. a) mcp6s92-e/ms: two-channel pga, msop-8 package. b) mcp6s92t-e/ms: tape and reel, two-channel pga, msop-8 package. a) mcp6s93-e/un: two-channel pga, msop-10 package. b) mcp6s93t-e/un: tape and reel, two-channel pga, msop-10 package. part no. -x /xx package temperature range device data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recommended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 792-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products. downloaded from: http:///
mcp6s91/2/3 ds21908a-page 38 ? 2004 microchip technology inc. notes: downloaded from: http:///
ds21908a-page 39 ? 2004 microchip technology inc. information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application m eets with your specifications. microchip makes no representations or war- ranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchips products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic, and smartshunt are registered trademarks of microchip technology incorporated in t he u.s.a. and other countries. amplab, filterlab, mxdev, mxlab, picmaster, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, application maestro, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, migratable memory, mpasm, mplib, mplink, mpsim, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powertool, rflab, rfpicdem, select mode, smart serial, smarttel and total endurance are trademarks of microchip technology incorporated in t he u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned her ein are property of their respective companies. ? 2004, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification contained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specifications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are co mmitted to continuously improvi ng the code protection features of our products. attempts to break microchips code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona and mountain view, california in october 2003. the companys quality system processes and procedures are for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchips quality system for the design and manufacture of development systems is iso 9001:2000 certified. downloaded from: http:///
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